Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. Some integrated circuit manufacturers are investigating electrodeposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
Copper damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes in a nonconductive substrate, such as a silicon oxide. A barrier layer, e.g., of silicon nitride or tantalum, is deposited next. An initial seed or strike layer typically comprising copper and having a thickness of about 20 nanometers (nm) to 200 nm is then deposited by a conventional physical or vapor deposition technique. The seed layer is used as a base layer to conduct current for electroplating thicker films. Thinner seed layers are preferred so as to reduce overhang and closure of very small features with metal from the seed layer. The seed layer functions as the cathode of an electroplating cell. Electrical contacts to the wafer are normally made at its edge. Since the seed layer is usually very thin, there is a significant resistive drop between the points of contact at the edge of the wafer and the center of the wafer. This is referred to as the “terminal effect”. When the system is operating in a regime in which the plating rate is determined by the magnitude of the current, the plating rate is greater at the edge of the wafer than at the center of the wafer. As a result, the plated layer often has a concave dish-shaped profile initially. As the thickness of the copper layer increases during plating, the terminal effect diminishes and the plated layer is deposited at a more uniform rate. U.S. Pat. No. 6,074,544, issued Jun. 13, 2000 to Reid et al., which is hereby incorporated by reference, teaches a method of electroplating on a semiconductor wafer using a low current density initially to reduce resistance drop between the edge of the wafer and the center of the wafer, and then increasing the current density after the metal layer has reached a predetermined thickness.
Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform as possible. This uniform profile is advantageous in subsequent etchback or polish removal steps, as well as uniform void-free filling of the trench structures. Prior art electroplating techniques are susceptible to thickness irregularities. Factors contributing to these irregularities include the size and shape of the electroplating cell, electrolyte depletion effects, hot edge effects, and the terminal effect.
Regarding the trend towards larger diameter wafers, it is generally understood that the deposition rate, as measured by layer thickness, can be maintained by scaling total current through the electrochemical reactor in proportion to the increased surface area of the larger wafer. Thus, a 300 millimeter (mm) wafer requires 2.25 times more current than does a 200 mm wafer. Electroplating operations are preferably performed by using a clamshell-type wafer holder that contacts the wafer only at its outer radius. Due to this mechanical arrangement, the total resistance from the edge of the wafer to the center of the wafer is proportional to the radius. Nevertheless, with the higher applied current at the edge of the larger wafer, which is required to maintain the same current density for process uniformity, the total potential drop from the edge to the center of the wafer is greater for the larger diameter wafer. This circumstance leads to an increased rate of deposition that increases with radius where deposition is measured by layer thickness. While the problem of increasing deposition rate with radius exists for all wafers, it is exacerbated in the case of larger wafers.
The introduction of damascene metallization for copper interconnects has led to the development and modification of processes for 0.13 microns (μm) and smaller design rules. The implementation of new process flows has caused new device-killing defect formation, as well as nuisance defects, which interfere with the ability to identify accurately the device-killing defects. In copper damascene metallization, defects generally arise during the three main process sequences: deposition of barrier and seed layers; electrofill operations, including pre- and post-anneal; and chemical mechanical polishing (CMP). The ability to analyze and monitor defects on plating films requires the optimization of metrology. Measuring defects on copper deposits is difficult, in part, because the subtle variations in surface morphology are highly sensitive to process conditions. For example, the KLA-Tencor AIT II is an optical contrast apparatus that is particularly sensitive for measuring films thinner than 1 μm. Combined with a defect-review capability (e.g., optical microscope or SEM), the AIT II is useful for identifying defects. Measuring copper defects typically requires a trade-off of sensitivity to accommodate signal-to-noise ratios. False readings result from the high reflectivity of metal films, thereby reducing instrument sensitivity and causing inaccurately low defect counts.
Critical post-plating in-film killer defects in electroplated copper layers include pits, craters, and voids, which typically form during the electroplating process or during the post-plate anneal steps. Another type of defect are single isolated protrusions. Single isolated protrusions can usually be eliminated during CMP. Nevertheless, single isolated protrusions are nuisance defects because they hinder the identification of critical defects, such as pits. Therefore, the elimination of single isolated protrusion defects is important for accurate and reliable identification of critical defects.
DC electroplating tends to result in undesirable “hump” development over small features, for example, features less than one micron. Such humps may have a step height of, for example, more than 0.5 microns when the target plated thickness is 1.0 micron. Non-uniform surfaces commonly lead to over polishing in subsequent chemical mechanical polishing (“CMP”) operations, which adversely affects the integrated circuits being manufactured.
In DC electroplating, additives such as accelerators, suppressors, and levelers are typically included in the electrolytic plating solution to improve electroplating behavior by, among others, enhancing chemical reactions, improving surface deposition, improving thickness uniformity, and enhancing filling of high aspect ratio features. A conventional electrolytic plating solution also includes sulfuric acid to provide high conductivity to the electrolyte and chloride ions to enhance additive performance. The presence of additives, sulfur ions, or chloride ions in an electrolytic plating bath, however, often leads to occlusion of undesired material in the deposited metal layer.
Various electroplating schemes have been suggested for avoiding problems commonly encountered in electroplating of metal, particularly copper, in integrated circuit fabrication. For example, U.S. Patent Application Publication No. US 2002/0056645 A1, published May 16, 2002, discloses a method using a sequence of anodic and cathodic current pulses to deposit a metal layer. U.S. Pat. No. 5,972,192, issued Oct. 26, 1999 to Dubin et al., discloses both unipolar (i.e., forward) pulse plating and forward-reverse pulse plating of copper. U.S. Pat. No. 6,432,821 B1, issued Aug. 13, 2002 to Dubin et al., discloses several electroplating programs combining forward and reverse current pulses. Similarly, U.S. Pat. No. 6,440,289 B1, issued Aug. 27, 2002 to Woo et al., teaches both forward-pulse and forward-reverse pulse techniques for electroplating. Reverse currents often introduce defects in plated films as a result of irregular etching of the metal (e.g., copper) or irregular desorption of additives from the metal surface.